Slip detection system

ABSTRACT

A system for detecting excessive slip between the speed of an ac. motor and the speed of an a-c. generator supplying power to the motor at a variable frequency. Transducers associated with the motor and the generator produce pulses at frequencies proportional to the speeds of the motor and the generator, respectively. The periods Tm and Tg of these two series of pulses are measured by applying clock pulses to a counter during each period, so that the number of clock pulses counted during each period is proportional to the duration thereof. The pulses applied to the counter during the period Tm are counted up, and the pulses applied during the period Tg are counted down, so that the resulting output of the counter represents the difference (Tm - Tg). The count representing the period Tm is stored in a separate register, and the number representing Tm is then repetitively subtracted from the number representing (Tm - Tg) until the remainder is reduced to zero. The number of subtraction steps required to reduce the remainder to zero is counted to provide a number representing the quotient (Tm -Tg)/Tm. This quotient represents the per cent slip of the motor, and is compared with a preselected per cent slip limit determined by the setting of a series of thumbwheel switches. If the measured per cent slip value exceeds the preselected limit, an output signal is generated for actuating an alarm or other suitable utilization device so that the excessive slip condition can be corrected. Computation of the actual per cent slip is carried out by digital signal processing on a rapidly iterating basis so that the system provides a substantially instantaneous indication of any change in the percent slip. The system includes a number of auxiliary features for detecting various malfunctions and for resetting the system in response to both internal and external command signals.

United States Patent 1191 Barrett et al SLIP DETECTION SYSTEM 751Inventors: William J. 3 Barrett, Rockford, 111.;

Harold Green, Middleton, Wis.

[73] Assignee: Woodward Governor Company, Rockford, Ill.

22 Filed: Feb. 5, 1973 21 Appl. No.: 329,697

Primary Examiner-T. E. Lynch Attorney, Agent, or Firm-Wolfe, Hubbard,Leydig,

Voit & Osann, Ltd.

57 ABSTRACT- A system for detecting excessive slip between the speed ofan a-c. motor and the speed of an a-c. generator supplying power to themotor at a variable fre- 1111 3,832,609 5] Aug. 27, 1974 quency.Transducers associated with the motor and the generator produce pulsesat frequencies proportional to the speeds of the motor and thegenerator, respectively. The periods T, and T,, of these two series ofpulses are measured by applying clock pulses to a counter during eachperiod, so that the number of clock pulses counted during each period isproportional to the duration thereof. The pulses applied to the counterduring the period T,, are counted up, and the pulses applied during theperiod T, are counted down, so that the resulting output of the counterrepresents the difference (T T,,). The count representing the periodT,,, is stored in a separate register, and the number representing T isthen repetitively subtracted from the number representing (T T until theremainder is reduced to zero. The number of subtraction steps requiredto reduce the remainder to zero is counted to provide a numberrepresenting the quotient (T ,,)/T,,,. This quotient represents the percent slip of the motor, and is compared with a preselected per cent sliplimit determined by the setting of a series of thumbwheel switches. Ifthe measured per cent slip value exceeds the preselected limit, anoutput signal is generated for actuating an alarm or other suitableutilization device so that the excessive slip condition can becorrected. Computation of the actual per cent slip is carried out bydigital signal processing on a rapidly iterating basis so that thesystem provides a substantially instantaneous indication of any changein the percent slip. The system includes a number of auxiliary featuresfor detecting various malfunctions and for resetting the system inresponse to both internal and external command signals.

31 Claims, 11 Drawing Figures mama, 10271314 3.832.609

MET 2 U 8 [war war Pmmanmmm 3.832509 Q MET-7N 8 [N0 0/- I; Jar/v; I flmzwzi\ Y (42 H H II I] II I] H II. I] II II II [I II ,II [I H II [I [I IIII H w WW 4624 j I f] arr zzrr J 477* 4 f 7 J77 H m7 Q w m 7? i s, m m1% E zkaz/r i w H g" me E -jj fi iL m F1 F1 SLIP DETECTION SYSTEMDESCRIPTION OF THE INVENTION The present invention relates generally tosystems for signaling the percentage difference between the frequenciesof two recurring signals of variable frequency and, more particularly,to a system for signaling the percentage difference between the speed ofan a-c. motor and the speed of an alternator or generator supplyingpower to the motor at a variable frequency.

In the case of an a-c. motor energized with alternating current from analternator or generator of variable speed, slip" is defined as thedifference between the alternator or generator speed (N,,) and the motorspeed (N,,,) divided by the alternator or generator speed. This quotientmultiplied by 100 gives the per cent slip, or

In certain applications of such systems, it is important to detect whenthe slip exceeds a certain limit. For example, in a hydroelectricsystem, excess generator capacity may be used during periods of lowdemand to drive one of the alternators as a synchronous motor to pumpwater back uphill for use in periods of high demand. Excessive slipping,especially likely during startup, in such a system produces abnormallyhigh currents and correspondingly high temperatures. Consequently, if anexcess slip condition occurs, the equipment must be allowed to cool fora relatively long period, e.g., to 12 hours, before starting up again.Thus, it is extremely desirable to detect when the slip exceeds apredetermined limit so that the generator can be controlled in speed andfrequency to limit slip of the motor.

It is a primary object of the present invention to provide a slipdetection system which continuously monitors the magnitude of slip in amotor-generator combination, and actuates a utilization device such asan alarm or automatic shut-down device whenever the slip exceeds apredetermined limit.

i It is another object of the invention to provide a slip detectionsystem of the foregoing type which has ahigh degree of accuracy andreliability over a relatively wide speed range.

A further object of the invention is to provide a sli detection systemof the type described above which permits convenient manual adjustmentof the predetermined limit of slip detected by the system.

Still another object of the invention is to provide such a slipdetection system which continually computes the per cent slip andprovides a substantially instantaneous indication of whether the percent slip is above or below a predetermined limit. A related object isto provide such a system which is characterized by high reliability andimmunity from aging or drift by virtue of digital signal processing on arapidly iterating basis.

A still further object of the invention is to provide such a slipdetectionsystem which immediately senses a failure of the motor to startand provides an indication of such failure.

Yet another object of the invention is to providesuch a slip detectionsystem which continuously monitors the primary inputs to the system andprovides a substantially instantaneous indication of any malfunctionthat results in an interruption of such inputs.

Other objects and advantages of the invention will be I apparent fromthe following detailed description taken in connection with theaccompanying drawings, in which:

FIG. 1 is a block diagram of a slip detection system embodying theinvention;

FIG. 2, constituted by FIGS. 2a and 2b when joined, is a more detailedblock and circuit diagram of the system illustrated in FIG. 1;

FIG. 3 is a moredetailed block diagram of the computing portion of thesystem illustrated in FIG. 2;

FIG. 4 is a timing diagram illustrating the signals in that portion ofthe system of FIG. 2 which measures the period T,,,;

FIG.'5 is a-timing diagram illustrating the signals in that portion ofthe system of FIG. 2 which controls the signals applied to the countup'input of the up-down counter;

FIG. 6 is a timing diagram illustrating the signals in that portion ofthe system of FIG. 2 which controls the signals applied to the countdown input of the updown counter;

FIG. 7 is a timing diagram illustrating the signals in that portion ofthe system of FIG. 2 which controls the timing of the computingoperations;

FIG. 8 is a timing diagram illustrating the signals in the output andreset portions of the system of. FIG. 2;

FIG. 9 is a timing diagram illustrating the signals-in the start-upcheck portion of the system of FIG. 2; and

FIG. 10 is a timing diagram illustrating the signals in the input signalmonitoring portion of the system of FIG.'2.

While the invention will be described in connection with a preferredembodiment, it will be understood that it is not intended to limit theinvention to that embodiment. On the contrary, it is intended to coverall alternatives, modifications and equivalents as may be includedwithin the spirit and scope of the invention as defined by the appendedclaims.

Before considering the slip detection system illustrated in thedrawings, it will be helpful to note the symbols and conventions whichhave been employed in those figures to diagrammatically representdifferent logic devices and signals. In this connection, the systemshown in the drawings operates on a binary logic basis, i.e., eachsignal which is produced and responded to may have either a binary l or0 value. These might be, for example, voltage levels of 12 volts andzero volts, respectively, which is positive logic since the mostpositive logic voltage levelis defined to be the logical I state, whilethe most negative logic voltage level is defined to be the logical 0state. The system illustrated generally responds affirmatively to binaryl signals, but when any given signal has a binary 0 value, that willnormally produce no response (although a response to a binary 0 signalmay be produced in certain instances.)

The term flip-flop is used herein to designate a device that exhibitstwo different stable states. The illustrative system utilizes twodifferent types of flip-flops, namely the D-type and the JK-type. TheD-type flipflop is characterized by a single data (D) input and a clock(C) input, and it may have either or both Q and Q outputs available. Thedata input is a synchronous input, i.e., it does not cause an immediatechange in the output, but rather requires the presence or occurrence ofa clock pulse at the clock input to generate a change of state in theoutputs. When the flip-flop is clocked by the occurrence of a clockpulse at the clock input, the binary signal present at the data input istransferred to the Q output, and the Q output is always the complementof the Q output. For example, if the signal at the data input is abinary 1 when the flip-flop is clocked, the Q output is a binary 1signal and the Q output is a binary signal after clocking. This type offlip-flop may also have asynchronous preset (P) and/or clear (Cr) inputswhich are overriding controls that inhibit normal operation and causethe Q output to go to either a binary 1 or 0 level, depending on whichinput is present.

The JK-type flip-flop has two data inputs, J and K, and only a singleclock input. When the signals present at the J and K inputs are. atdifferent binary levels when the flip-flop is clocked, the signalpresent at the J input is transferred to the Q output, and the 0 outputis always the complement of the Q output. When the binary 0 signals arepresent at both the J and K inputs when the flip-flop is clocked, theoutputs remain unchanged at the. levels existing prior to clocking. Whenbinary 1 signals are present at both the J and K inputs when theflip-flop is clocked, the outputs always change state in response to theclocking signal. As in the case of the D- type flip-flop, the JK-typeflip-flop may also have asynchronous preset (P) and/or clear (Cr) inputswhich override the other inputs and cause the Q output to go to either abinary I or 0 level, depending on which input is present.

NAND gates and NOR gates have been illustrated by the conventionalsymbols exemplified by the gates 55 and 38, respectively, in FIGS. 2aand 2b. As is well known, the output of the NAND gate is always a binary1 signal except when all inputs are binary I signals, in which case theoutput becomes a binary 0 signal. Cons versely, the output of the NORgate is always a binary 0 signal except when all inputs are binary 0signals, in

which case the output becomes a binary 1 signal.

In FIGS. 2 through 9, certain logic signals appearing on variousconductor lines are designated by alphabetical symbols. The letterschosen for these symbols sometimes represent words or phrases whichloosely define the significance or function of the designated signal.Because the relationships between these symbols and the functions of thesignals the designate may aid in understanding the description whichfollows, these relationships will be listed here:

Alphabetical Symbol Function AST Indicates that no computation has beencompleted within n phase A signals. Used to generate a reset and preventinadvertent lock up of the unit.

Borrow from most significant bit of counter 52.

Used to clear both motor input flip- .flops 36 and 40 on GO or with RST.CLI First clock signal CL2 Second clock signal, out of phase with firstclock signal.

Carry output from adder 75. Used to indicate completion of each addingstep and when sum goes to zero Used to transfer output of adder 75 toup-down counter 52 during calculate phase of measurement cycle. Occursbefore RTR.

Output of gate 80 used to increment counter 81 by one in response toeach CRY indicating completion of an adding step.

BOR

CLEARX CRY CTR

DEC

Function 5 FFB FFR GCLK OVF PHA

PHAD

PHAX

PHB

PHBD PHBX PST.

RST

RTR

SMC

SOK

SRT STRT SUC SWD

SWU

Down count provides CLI input to count-down input of up-down counter 52during measurement of interval between generator pulses Output offlip-flop I25 used to indicate loss of P,, or P,,.

A selective reset pulse applied only to flip-flops 92, III, H2 and I25.FFR is activated by power on or remote pushbutton but not by GCLK.

The clock generated by the lack-of CRY from adder 75. Applied to theoutput flip-flop 92, and is used to clock the output to the. statedemanded by the output of the comparator. GCLK is gated with CL2.

ls used to start the measurement cycle if a motor pulse is receivedbefore the initial counter 74 reaches the preset number of generatorpulses. Power on signal used to generate resets RST and RST.

Generates GCLK when CRY indicates zero sum in adder 75.

Indicates too many generator pulses have been received without a motorpulse. ls used to generate an error signal toactivate alarm.

Generates SRT on end of computation cycle or on hand-up,

Output of single shot I20 used to monitor P,,,.

Output of single shot I21 used to monitor Signal from the motor afterbeing passed through the Schmitt trigger 34. Prestart signal used togenerate a complete reset of the detector. Generates both RST and FFR.

A universal reset signal generated by power on, GCLK or a remote pushbutton. All control flip flops except 92, l l I, 112 and I25 are clearedby RST.

Used to transfer information into register 73 during computation ofphase of operation.

Is 0 when both PHAD and PHBD are I. Indicates detector is in computationphase. Enables the register and counter transfers RTR and CTR.

Sets flip-flop l I l to enable start of detector if Pm is receivedbefore LKOUT indicates error.

Trigger signal for reset.

A signal which, when 0, begins counting generator pulses. During startup, the rise of STRT indicates a measurement cycle is under way. STRTgoes to 0 on reset and I if initial counter 74 contains too manygenerator pulses before receiving a motor pulse. The combination of CMand the phase B measurement cycle. Indicates a countdown operation.

The gated count-down signal. ls active after PHB and before PHBD. Isapplied to the count-up input of counter 52 if underflow occurs duringcount-down. Enables application of SUC to countdown input of counter 52in response to when neither PHBD nor SWU is I.

A signal indicating that a borrow has been generated by the counter.

TPE Detects coincidence of CS1 and CS2.

Goes to 1 when P or P, lost.

UCT Up count. Provides CLl input to count up input of counter 52 duringmeasurement of time between motor pulses.

UP Up count provides CLl input to count-up input of counter 32 duringmeasurement of interval between motor pulses.

UPF The clock applied to the counter 74 during start-up check.

UPS The up signal generated by CLl and PHA.

UPT The controlled count-up signal which is gated by the completion ofthe motor measurement operation.

The complement-of any signal designated by a given alphabetical symbolis conventionally designated by the same symbol with a superimposed baradded. For example, when the signal PHA is a binary l or 0, the signalPI-IA is a binary or 1 respectively.

Turning now to the block diagram of FIG. 1, the invention is illustratedin one exemplary application for detecting the percentage slip between asynchronous motor 5 energized by. a three-phase alternator 6 (referredto hereinafter as the generator). Although the invention has a widevariety of different applications, in the particular systemillustratedthe alternator 6 is driven by a prime mover 7 powered by an energymedium source 8 via a governor 9. For example, the illustrative systemmay represent a hydroelectric system in which the prime mover 7 is ahydraulic turbine powered by water pressure as the energy medium, withthe water control valve representing the governor 9. In such a system, ahuman operator normally adjusts a set point control 9a to adjust thegovernor 9 to control the speed of the prime mover 7 and thus thealternator 6. During start-up of the motor 5, it is particularlyimportant that the operator adjust the set point control 9a to bring thealternator 6 up to speed at a rate which does not produce excessive slipbetween the motor 5 and the alternator 6, so as to avoid thedifficulties described previously.

In accordance with one important aspect of the present invention, theslip detection system includes .means for generating signalsrepresenting the speeds of the motor and the generator, and computingmeans responsive to such signals for producing an output signalrepresenting K( T,,, T,,)/T where K is a predetermined constant, T, isthe period of rotation of the motor, and T is the period of rotation ofthe generator. Thus, in the system of FIG. 1, a pair of pulse generators10 and 11 produce two'series of pulses P,, and P (see, e.g.,

To solve this equation, the output of the detector 14 enables a gate 16to pass clock pulses from a source 17 to the count-up input of anup-down counter 18 during the period T,,,; at the end of the periodT,,,, the output of detector 14 disables the gate 16 so that the numberof clock pulses counted by the counter 18 represents the deviation ofthe period T,,,. This count is FIGS. 9 and 10) at frequenciesproportional to the. I

speeds of the motor 5 and the generator 6, respectively. Thus, thefrequency of pulses P,, represents the motor speed N,,,, while thefrequency of pulses P represents the generator speed N,,. The two seriesof pulses P,, and P from the generators 10 and 11 are applied to a pairof detectors l4 and 15 which produce output signals representing theperiods between successive pulses in each of the two series P and Prespectively. Thus, the outputs of the detectors l4 and 15 represent theperiods T, and T which are inversely proportional to the correspondingspeeds N,,, and N Consequently, the percent slip equation describedpreviously can be expressed as follows:

stored in a T register 19. When the gate 16 is disabled,

it also conditions a gate 20 to be enabled by the next T signal from thedetector 15. As a result, clock pulses from the source 17 are passedthrough the gate 20 and applied to the count-down input of the counter18 during the period T,,, at the end of which the gate 20 is disabled.

Since the clock pulses transmitted to the counter 18 are counted upduring the period T and down during the period T,,, the net countaccumulated in the counter 18 at the end of both counting operations isthe difference (T T which is the numerator or dividend in the percentslip tenn (T,, T,)/T,,,. This number (T,,, T is stored in a register 21for use in a subsequent division operation to obtain the quotient (T,,Tn)/T,,,. To carry out the desired division, the T count in the register19 is successively subtracted from the (T,, T count in the register 21until the remainder reaches zero (or goes negative), and the number ofsubtraction steps required to reduce the remainder to less than T is thedesired quotient.

Thus, in the system illustrated in FIG. 1, the dividend (T T is passedthrough a multiplier to produce an output signal representing 100 (T Tand this product is fed to a subtracting unit 23 which successivelysubtracts T,, from 100(T T Each time a subtraction step is carried out,the subtracting unit 23 increments a counter 24 by one. When therepetitive subtraction process results in a remainder of less than T,,,,using binary numbers, the subtraction unit 23 produces a borrow" outputwhich stops the counter 24, and the count accumulated in the counter 24at this point represents the desired quotient 100( T,,, ,,)/T,,,.

In accordance with another important aspect of the invention, means areprovided for generating a signal representing a preselected maximumlimit for the percentage of slip between the generator and motor, andfor producing an excess slip signal whenever the measured percentageslip value exceeds the value of the preselected maximum limit. Thus, theillustrative system of FIG. 1 includes a set of thumbwheel switches 26that can be set to different positions to preselect a desired maximumslip value. In order to determine whether the computed slip exceeds thepreselected maximum value determined by the settings of the switches 26,the output of the counter 24 is applied to a comparator 25 whichreceives its other input from the switches 26. Whenever the measuredslip number from the counter 24 exceeds the preselected maximum numberfrom the thumbwheel switches 26, the comparator output actuates autilization device 27. The utilization device 27 may be any suitablemeans for utilizing the output signal from the comparator 25, such as analarm device for alerting the operator to the fact that an excess slipcondition exists so that he can shut down the system or perhaps adjustthe governor set point control 911 accordingly, or an automatic controlsystem for adjusting the governor set point automatically in response tothe comparator output signal.

' Each time the counter 24 is stopped at the end of a dividingoperation, a reset signal generator 28 is actuated to produce a resetsignal which resets the two detectors l4 and 15 and the counter 18 tocondition the system for another operating cycle. Thus, the counter18'counts another pair of periods T and T and the computing operation isrepeated to determine a new quotient lO(T,,, g)/T,,,.

In accordance with one particular aspect of the invention, the motor andgenerator signals P, and P are both continuously monitored to'insurethat the signals remain present during operation of the slip detectionsystem. Without such monitoring, the termination of one of these inputsignals due to a malfunction, for example, could result in a calculationof zero slip or some other error which could mislead the operator. Thus,the signals P and P, are both applied to a monitor circuit 29 which isconnected to the utilization device 27 for automatically actuating thealarm in response to termination of either one of the input signals P,and P Turning next to FIGS. 2a and 2b, there is shown in more detail anexemplary system of the type illustrated generally in FIG. '1. Theprimary input signals representing the generator speed N and the motorspeed N,, are in digital. form, comprising series of pulses P, and P(FIGS. 4, 9 and generated at frequencies proportional to the speeds ofthe generator and'the motor, respectively. Transducers for generatingsuch pulses are well known and may comprise Hall effect devices havingtoothed wheels 30 and 31 carried by the generator and motor shafts forinducing signals, such as signal f,,, in FIG. 4, in stationary pick-updevices 32 and 33 at frequencies proportional to the speeds of therespective shafts. In the illustrative system, the pick-up devices 32and 33 are connected to Schmitt triggers 34 and 35 for converting thesinusoidal signals induced in the pick-up devices to square pulses P andP as illustrated in FIGS. 4, 9 and 10. A Schmitt trigger is aconventional regenerative bistable circuit whose state depends on theamplitude of the inputvoltage so that it can be used for squaring asinusoidal input. Simple single pole filters formed by the RC networksRlCl and R2C2 on the inputs of the Schmitt triggers 34 and 35,respectively, remove induced noise from the output signals of thepick-up devices 32 and 33.

In order to convert the two series of pulses P and P to signalsrepresenting the periods T, and T,,, between pulses, which areproportional to the periods of rotation of the generator and motor, theoutput pulses P and P,,, from the Schmitt triggers 34 and 35 are appliedto the clock inputs of a pair of conventional .IK-type flip-flops 36 and37, respectively, operated in the toggle mode. Thus,- a binary 1 signalis applied to both the J and K inputs of each flip-flop so that theoutputs Q and Q change state whenever the flip-flop is clocked; in theillustrative system the Q and Q outputs of the flip-flops 36 and 37change state in response to each negative transition at the clock input,i.e., at the trailing edge of each positive-going pulse P or P,,, sothat the outputs of the flip-flops 36 and 37 represent the periods T andT between successive pairs of pulses P, and P respectively. Theresulting Q output of the flip-flop 36 is illustrated in FIG. 4 assignal PHAX; though not illustrated, the Q output of flip-flop36 isdesignated PHAX, the Q output of flip-flop 37 is designated PHBX, andthe Q output of flip-flop 37 is designated PI-IBX. Prior to applicationof the pulses P and P,,, the two flip-flops 36 and 37 are cleared by therespective output signals from NOR gates 38 and 39, which will bedescribed in more detail below. I

For the purpose of synchronizing the signals representing T, and T, withan internal clock signal, the Q and Q outputs of the flip-flops 36 and37 are connected to theJ and K inputs, respectively, of'a second pair ofJK-type flip-flops 40 and 41. The internal clock signal,

designated signal CL2 and illustrated in FIG. 4, is applied to the clockinput of both the flip-flops 40 and 41. Each time one of the flip-flops40 or 41 is clocked, the state of the J input thereof is transferred tothe Q output, and the state of the K output is transferred to the Qoutput; thus the Q and Q outputs of the flip-flops 40 and 41 areidentical to those of the flip-flops 36 and 37, respectively, exceptthat they are synchronized with the clock signal CL2. The Q output offlip-flop 20 is designated PI-IA (FIG. 4), the Q output of flip-flop 40is designated PHA (FIG. 5), and the Q output of flip-flop 41 isdesignated'PHB (FIG. 6).

' Assuming the flip-flop 40 has been cleared by the signal CLEARX (FIG.4) from the gate 38 and a binary 1 signal is present at the J input ofthe flip-flop 40, the Q output (PHA) from the flip-flop 40 rises from abinary 0 to a binary 1, and the Q output (PI-IA) drops from 1 to 0, inresponse to the next negative transition in the clock signal CL2. Theoutputs of the flip-flop 40 then remain at these levels until the Qoutput from flipflop 36 returns to the 0 level, after which the Q and Qoutputs of flip-flop 40 return to the 0 and 1 levels, respectively, inresponse to thenext negative transition in the clock signal CL2.

To measure the widths of the periods T,,, and T represented by theoutput signals from the flip-flops 40 and 41, the Q output signals fromthese flip-flops are used to control the gating of a second clock signalCLl to the count-up and count-down input terminals 50 and 51,respectively, of a 20-bit up-down binary counter 52. The pulses of theclock signal CLl are counted only during the intervals T, and T,represented by the signals PI-IA and PHB, respectively, so that theresulting counts are numerically proportional to the durations of theintervals'T and T Furthermore, the pulses gated into the counter 52 bythe signal PHA representing T, are counted up, and the pulses gated intothe counter by the signal PHB representing T, are counted down so thatthe resulting net count is numerically proportional to the difference TT which is the numerator or dividend in the per cent slip equationdescribed previously.

Turning now to a more detailed description of the gating arrangementbetween the Q outputs of the flipflops 40 and 41 and the counter 52, theQ output from the flip-flop 40 and the inverted clock signal CLl areapplied to a NOR gate 53 connected to the count-up input of the counter52, while the 0 output from the flip-flop 41 and the inverted clocksignal CLl are applied to a NOR gate 54 connected to thecount-downinput. When the Q output from either flip-flop 40 or 41 is abinary 1 signal, the clock signal CLl does not pass the correspondingNOR gate 53 or 54, i.e., the output of the gate 33 or 34 is maintainedat the binary 0 level. However, when the Q output of one of theflip-flops 40 or 41 is changed to a binary 0 signal, the clock signalCLl passes through the corresponding NOR gate 53 or 54 to produce thecomplement thereof (CLl) at the gate output, i.e., the output of thegate 53 (signal UPS in FIG. 5) or 54 (signal SUC in FIG. 6) switchesbetween the binary 0 and 1 levels in synchronism with the clock signalCLl.

For the purpose of controlling application of the output signal UPS fromthe gate 53 to the counter 52, this signal UPS is applied to a NAND gate55 which also receives the Q output from D-type flip-flop 57. Althoughthe signal UPS is generated repetitively in response to the toggling ofthe flip-flop 36, it is necessary to block the application of the signalto the counter 52 while the width of the period T, is beingmeasured andwhile the computing portion of each cycle of operation is carried 5 outto determine the value of the percent slip ratio (T T,,)/T,,,. For thispurpose, a binary 1 signal GO (FIG. 4), from a source to be describedbelow, .is normally applied to the data input of the flip-flop 57, whilethe Q output (PHA) of the flip-flop 40 is applied to the clock input.The D-type flip-flop 57 is clocked by a positive transition at its clockinput, so the binary l at the data input is transferred to the Q outputin response to the trailing edge of signal PHA at the end of the periodT,,,. The Q output of the flip-flop 57 is always the inverse of the Qoutput, so the Q output becomes a binary signal when the Q output goesto the binary 1 level. These Q and Q outputs are designated signals PHADand PHAD, respectively, and are illustrated in FIGS. 4 and 5. 1

Since the data input to the D-type flip-flop37 is a continuous binary 1signal during steady state operation, the Q and Q outputs thereof remainat the binary l and 0 levels until the flip-flop 57 is cleared by areset signal (designated RST in FIG. 4) applied to its clear input atthe end of each complete operating cycle. Thus, the signal PHAD appliedto the NAND gate 55 is a binary 1 signal during one period T,,,, therebyen-- abling transmission of the clock signal CLl to the count-up input50 during that period, and then is switched to a binary 0 signal at theend of the period T, to prevent thetransmission of any further signalsto the count-up input 50 until the flip-flop 57 is cleared at the end ofa complete operating cycle.

During the period T,,, whenthe gate 55 is enabled by the coincidence ofbinary l signals from both the gate 53 and the Q output of flip-flop 57,it produces an output signal UPT (FIG. 5) which is the complement ofsignal UPS during one period T,,,. This output signal is applied to aNAND gate 58 which receives its other 40 input signal SWC (FIG. 5) froma NAND gate 59. The purpose of the gate 59 is to apply the normalcountdown input signal SUC to the count-up input 50 wheneverthe counter52 counts down to zero before the end of the period T,,, which occursonly when the 45 period T, is greater than T Of course, this result canbe obtained only when the motor speed is greater than the generatorspeed, which may happen in a transient condition. Such an event isdetected by applying the borrow output signal BOR (FIG. 6) of the mostsignificant position in the counter 52 to the clock input of a J K-typeflip-flop 60 having a continuous binary 1 signal applied to its J and Kinputs, so that the 0 output signal SWU (FIGS. 5 and 6) of the flip-flop60 becomes a binary 1 whenever the flip-flop 60 is clocked by a negativetransition in the signal BOR. The resulting binary 1 signal SWU enablesthe. gate 59 to pass the remainder of the count-down pulses (illustratedby signal SWC in FIG. 6) through the gate 58 to the count-up input 50,while blocking the transmission of any further pulses to the count-downinput 51. Consequently, the counter 52 determines the absolute value ofthe term T T regardless of whether T, or T, is greater.

Whenever the gate 58 receives an operative count-up 65 signal UPT orSWC, it produces a corresponding output signal UP (FIG. 6) which ispassed through an inverter 61 to provide the final signal UP (FIG. 6)that is applied to the fcounvup input 50. The counter 10 has a capacityof 20 bits, which means that it can count from zero through 1,048,575.

Turning next to the count-down phase of the counting operation thatdetermines the, value of (T T the output of the gate 54 when the Qoutput of the flip-' flop 41 is a binary 0 signal is illustrated assignal SUC in FIG. 6. This output signal SUC is applied to a NAND gate62 which also receives the output signal (FIG. 6')

from a NOR gate 63. The inputs to the NOR gate 63 are the signal SWUdescribed previously, and the Q output signal PHBD from a D-typeflip-flop 64. As described previously, the purpose of the signal SWU isto transfer the signal SUC from the count-down input to the count-upinput of the counter 52 in the event that the counter reaches zerobefore the end of the period T,,. For this purpose, the binary 1 outputsignal SWU produced by the flip-flop in response to a BOR signal causesthe output of the gate 63 to go to the binary 0 level, thereby disablingthe gate 62 to interrupt transmission of the signal SUC to thecount-down input 31.

The purpose of the flip-flop 64 is to control application of the signalSUC to the counter 52 when the BOR signal is 0. Although the signal SUCis generated repetitively in response to toggling of the flip-flop 37,this sig nal is to be applied to the counter 52 only during a singleperiod T, following each period T in which the signal UP is applied tothe counter. For this purpose, the signal GO normally applies a binary 1signal to the data input of the flip-flop 64, while the Q output (PI-IB)of the flip-flop 41 is applied to the clock input. The D- type flip-flop64 is clocked by a positive transition at its clock input, so the binaryl at the data input is transvferred to the Q output in response to thetrailing edge of signal PHB at the end of the period T The Q output ofthe flip-flop 64 is always the inverse of the Q output, so theQ outputbecomes a binary 0 signal when the Q output goes to the binary 1 level.These Q and Q out- .puts are designated signals PHBD and PHBD,respectively, and PHBD is illustrated in FIGS. 6 and 7.

Since the data input to the D-type flip-flop 64 is a continuous binary 1signal during steady state operation, the Q and Q outputs thereof remainat the binary l and 0 levels, after being clocked by signal Pl-IB, untilthe flip-flop 64 is cleared by the reset signal RST applied to its clearinput at the end of each complete operating cycle. Thus, the signal PHBDapplied to the NOR gate 63 is a binary 0 signal during one period T,,,thereby producing a binary 1 output signal SWD for enabling the gate 62to transmit the clock signal CLl to the count-down input 51 during thatperiod, and then is switched to a binary 1 signal at the end of theperiod T, to prevent the transmission of any further signals to thecount-down input 51 until the flip-flop 64 is cleared at the end of acomplete operating cycle. The final output of the gate 62 is designatedsignal DN and is illustrated in FIG. 6.

In order to delay the generation of the first signal representing aperiod T, until after generation of the first signal representing aperiod T in each operating cycle, the two flip-flops 37 and 41 whichgenerate the signals PI-IBX and PHB representing T, are disabled by theapplication of steady signals to their clear inputs. This is done solong as the signal PHAD exists and until the first signal. PI-IArepresenting T,,, has been generated.

flip-flops 37 and 41 to inhibit operation thereof. At the end of thefirst period T measured by the signal PHA, however, the signal PI-IAD isswitched to the binary level, thereby producing a binary 1 output signalfrom the gate 39 to enable the flip-flops 37 and 41 so that theseflip-flopsinitiate the measurement of the period T the next timethe-signal P, is switched to the binary 1 level. As a result of thisdelay in the enabling of the flip-flops 37 and 41, the transition in theoutput PI-IBD of flip-flop 64 indicating the end of the first period T,does not occur until after the transition in the output of flip-flop 57indicating the end of the first period T Moreover, the first transitionin the signal PHB does not occur until after the first period T has beenmeasured, even though the signal P,, is generated previously, so thatapplication of the clock signal CLl to the count-down input 51 via gate54 (controlled by signal PHB) is delayed until after measurement of thefirst period T,,,. I

In addition to terminating the application of clock pulses to thecount-up input 50 at the end of the period T and initiating measurementof the period T the signal PI-IAD is used to cause storage of the numberrepresenting the width of the period T in al 6-bit register 65 (FIG.2b). Thus, the signal Pl-IAD strobes the most significant 16 bits in thecounter 52 into the register 65 after clock pulses have been countedupwardly for one period T,,,, and the register 65 then holds a numberproportional to the duration of T,,,. Since the four least significantbits in the counter 52 are not transferred to the register 65, thenumber stored in the register 65 is actually the number representing T,,shifted four binary places to the left, which is equivalent to dividingthe number by 16. The purpose of this division by 16 will be explainedbelow.

When measurement of both periods T,,, and 7}, is completed, there iscoincidence of the Q outputs of both the flip-flops 57 and 64 (signalsPI-IAD and PI-IBD) at the binary 1 level for the first time. Theseoutputs are both connected to a NAND gate 70 so that the coincidence ofthe binary l signals at the inputs to the gate 70 produces a binary 0signal SMC (FIG. 8) at the gate output. This binary 0 signal SMC isapplied to a pair of NOR gates 71 and 72 to enable these gates to passclock signals CL2 and CLl, respectively. The output signal RTR (FIG. 7)from gate 72 leads the output signal CTR (FIG. 7) from the gate 71 andis applied to a 24-bit register 73 to strobe the 20 data bits from thecounter 52 and the 4 data bits from a supplemental counter 74 into theregister 73.

Referring to FIG. 3 for a more detailed description of the connectionsbetween the counters 53 and 74 and the registers 73 and 65, it can beseen that the counter 52 comprises five units 52a-52e having a capacityof four bits each, the register 65 comprises two eight bit units 65a and65b, and the register 73 comprises three eight bit units 73a-73c. Inresponse to the signal CTR, the four bits in the counter 74 and the fourleast significant bits in the counter 52, i.e., the four bits in unit52a, are transferred to the first register unit 73a, the eight next mostsignificant bits from counter units 52b and 520 are transferred to thesecond register unit 73b, and the six next most significant bits incounter units52d and 52e are transferred'to the third register unit 730.For reasons to be explained below, the two most significant bitlocations in the counter unit 52e and the regis ter unit 730 are notutilized. The effect of introducing the four bits from the supplementalcounter 74 into the four least significant positions in the register 73is to shift the number from the counter 52 four places to the left,which is the same as multiplying the number representing (T by 16. Aswill be seen from the ensuing discussion, this is the first step of athree-step multiplication process which ends up multiplying the numberrepresenting (T,,, T,,) by 1,024. This is an approximation of thedesired multiplier of 1,000, 100 of which is the multiplier included inthe percent slip equation, and the other 10 of which converts thedetected slip range of 0.1. to 9.9 percent to integers of l to 99. Theuse of 1,024 rather than 1,000 as a multiplier introduces acomputational error of 2.4 percent, which for practical purposes isnegligible in the illustrated system.

The next step in the computing process is to divide the numberrepresenting (T,, T by the number representing T,,, to obtain thequotient of (T,,, T,,)/T,,,. To

carry out the desired division, the T,,, count stored in v the two units65a and 65b of the 16 bit register 65 is repetitively subtracted fromthe T,,, T, count in the reg ister 73 until the latter count reacheszero (or goes negative), and the number of subtraction steps required toreach zero is the quotient (T )/T,,,. In the illustrative system, therepetitive subtractions are performed by successively adding the twoscomplement of the divisor (T from register 65) to the dividend ((T,,'T,,) from register 53) until the sum goes to zero; the number ofaddition steps is then the desired quotient. The twos complement of thedivisor is the complement of the binary number representing T with oneadded to it. For example, if the count representing the value of T, inregister 65 is 7, or 001 l l in binary form, its complement is 11000,and adding one. to this complement gives 1100], which is the twoscomplement. It is an axiom of binary arithmetic that the addition of thetwos complement of a first binary number to a second binary number givesthe same result as subtracting the first number from the second number,if the carry resulting from the addition process is ignored.

To perform the desired addition, the illustrative system includes aconventional binary adder having two parallel entry terminals X and -Yfor receiving signals digitally representing the two binary numbers tobe added, a carry input terminal for adding a signal representing anextra one to the sum of the X and Y inputs, parallel exit-sum outputterminals carrying signals digitally representing the sum of the numbersrepresented by the X, Yand carry inputs, and a carry output terminal 77carrying a signal representing any carries resulting from the additionprocess. As shown in more detail in FIG. 3, the adder 75 comprises sixfour bit units 75a-75f with adjacent units having their carry inputs andoutputs interconnected; each four bit unit has a four bit X input, afour bit Y input, and a four bit sum output.

Returning to a detailed description of the computation process, the twoscomplement of the binary number stored in the register 65 is formed bypassing the 16 bits stored in the register 65 through two multibitinverters 74a and 74b to the X inputs of the first four four bit units75a-75d of the 24 bit adder 75; applying binary l signals to the Xinputs of the last two four bit units 752 and 75f of the adder 75 tocomplete the entire ones complement of the binary number from register65; and then adding a one to the ones complement by applying a binary 1signal to the carry input 76 of the adder 75 to form the two scomplement. This formation of the twos complement in the adder 75 occursautomatically when the number representing T is transferred into theregister 65 upon the appearance of the signal PHAD, since the register65 is Connected directly to the adder 75 via the inverters 74a and 74bwithout any intermediate gates, and the binary l signals arecontinuously applied to the X inputs of the last two adder units 74eand74f and the carry input 76.

Addition of the twos complement of the T',,, number to the numberrepresenting (T T,) X 16 is effected automatically when the latternumber is strobed into the register 73 in response to the signal RTR.That is, the output of the register 74 is connected directly to the Yinputs of the adder 75, so that any number fed into the register 73 isimmediately transferred'to the adder 75. In the process of transferringthe number-representing (T T X 16 into the adder75, the number isshifted two more binary places to the left, which has the effect ofmultiplying the number by 4, so that the number actually-entered intothe adder represents (T T X64. This is the second step of the three-stepmultiplication process described previously. The third step is effectedby dividing the number representing (T,',, T X 64 by the numberrepresenting T,,,/ 16, which yields a quotient representing T T /T X1,024; it will be recalled that 1,024 isthe desired product of thethreestep multiplication.

Referring to FIG. 3 for a more detailed description of how the numberrepresenting (T T X 16 is shifted two binary places to the left in theprocess of being fed into the adder 75, it will be recalled that thelast two most significant bit locations in the bit counter were notutilized. Similarly, the last two most significant bit locations in theregister 73 are also not utilized. How ever, when the 18 bits of thebinary number in the register 73 are transferred to the adder 75, theyare transferred to the 18 most significant Y inputs to the adder, sothat in effect the two empty spaces are transferred to the right end ofthe adder 75, thereby transferring the binary number two binary placesto the left.

Each time a number is fed into the register 73, the adder 75 immediatelysums the X and Y inputs to produce a binary output signal representingthe sum of (i) the binary number representing (T T,-,) X 1,024 and (ii)the twos complement of the binary number representing T, (without thecarry). This multi-bit numberrepresenting output signal is applieddirectlyto, parallel entry input terminals of the counter 52 which isused as a holding register to store each new minuend temporarily duringthe repetitive subtraction (division) process. As long as the output ofthe adder 75 does not go to zero, the carry output 77 thereof is abinary l signal CRY (FIG. 8) which enables a NAND gate 80 to apply theclock signal CL2 to an eight bit binary codeddecimal (BCD) counter 81.The output of the gate 80 is designated signal DEC and is illustrated inFIG. 8. As will be apparent from the ensuing description, the timing ofthe repetitive subtraction steps effected by the adder 75 is controlledby the clock signals CLl and CL2, both of which have the same frequency.Thus, the clock pulses comprising the signal DEC are applied to thecounter 81 at the same rate at which the successive subtraction stepsare carried out, so that the counter 81 p is incremented once for eachsubtraction step, as long as the signal CRY remains at the binary 1level.

When the output of adder 75 is reduced to zero,' the carry" output CRYbecomes a binary 0 signal, indicating that the division process iscomplete and that the number stored in the counter 81 at that time isthe final quotient. "The switching of signal CRY to the binary 0 leveldisables the gate 80 to terminate the application of clock pulses to thecounter 81, thereby preventing any further incrementing of the counter81.

In order to prevent the counter 81 from responding to any clock pulsesapplied thereto prior to the first subtraction step, the signal SMC isapplied to the clear input of the counter 81 todisable the counter untilthe beginning of the computation period of each operating cycle. It willbe recalled that the signal SMC is the output of the gate 70, whichswitches from the binary l to the binary 0 level in response tocompletion of the measurement of both periods T, and T, in eachoperating cycle. As long as the signal SMC is at the binary 1 level, thecounter 81 is disabled, but as soon as the signal SMC drops to thebinary 0 level, the counter 81 is enabled to begin counting the clockpulses in signal DEC. As can be seen in FIG. 8, signal SMC drops to thebinary 0 level just prior to initiation of the first subtraction step bysignal RTR, which is synchronized with the clock signal CLl.

To cyclically repeat the binary subtraction process until the remainderis reduced to zero, at which time the carry output CRY of the adder 75becomes a binary 0 signal, the sum" output of the adder 75 isrepetitively strobed into the counters 52 and 74 by a signal CRTsynchronized with the clock signal CL2. More specifically, the SMCsignal from the gate enables the gate 71 to transmit the clock signalCL2 through an inverter 78 to the clock input of the counters 52 and 74to transfer the data from the adder 75 to the counters 52 and 74. As canbe seen in FIG. 7, synchronization of the signal CTR with the clocksignal CL2 causes it to trail the Ciel-synchronized signal RTR by abrief interval corresponding to the phase difference between the twoclock signals CLl and I CL2. Consequently, each time the signal RTRtransfers data into the adder 75 to initiate a subtraction step, a briefinterval is allowed for the data to settle, in the adder 75 before theadder output is fed back into the counters 52 and 74. This process isrepeated cyclically until the adder output is reduced to zero,indicating that the division process is complete.

It should be noted at this point that one of the purposes of thesupplemental counter 74 is to compensate for the difference in thecapacities of the 20 bit counter 52 and the'24 bit adder 75. Since theadder output includes 22 bits, and only 18 bits of the 20 bit capacityof the counter 52 are utilized, the supplemental four bit counter 74 isused to hold the four least significant bits of the adder output beforethey are transferred to the register 73.

To briefly recapitulate the computing process that is carried out duringthe computation period indicated in FIG. 7, the up-down counter 52 firstdetermines the difference (T T by counting up clock pulses during theperiod T, and then counting down clock pulses during the period T At theend of the up count, the number representing T is divided by 16 andstored in the register 65. At the end of the down count, the numberrepresenting (T T,,) is multiplied by 16 and stored in the register 73.Then to multiply (T T by a constant K 1,024 and divide the resultingproduct by T,,,: number T,,,/ l 6 stored in the register 65 is passedthrough the inverters 74a and 74b to form the ones complement thereof;this one's complement is applied to the X input of the adder 75 where itis added to the one applied to the carry input to form the two'scomplement of the number representing T,,,/l6;

and the number ,I6(T,,, T is multiplied by 4 and applied to the Y inputof the adder 75. The adder 75 instantaneously adds the binarynumbersrepresenting 64 (T,,, T and the twos complement of T,,,/ 16, which isthe same as subtracting T,,,/l6, from 64(T o), and the resulting sum isstored in the counter 52 (used as a holding register) until arrival ofthe next signal CTR. This subtraction process is repeated until theremainder is reduced to zero, so that the number-of subtraction stepscarried out represents the quotient 64(T T,,)/T,,,/ 16 or 1,024(T,, g)/m which is proportional to the per cent slip.

It will be understood that the computation process A recapitulated aboveis cyclically repeated at a fast rate, thereby providing a rapidlyiterating output representing the per cent slip. Although the durationof the computation period varies with changes in the magnitude of theper cent slip being computed, even the longest computation periodrequires only a fractionof a second in the high-speed digital signalprocessing system illustrated. Thus,'the system provides a highlyreliable and substantially instantaneous indication of any change in theper cent slip.

In keeping with the invention, the control system includes means forcontinually comparing the measured slip value with the pre-selectedmaximumvalue, and means for indicating when the measured slip valueexceeds the selected maximum value. Thus, in the illustrative system ofFIGS. 2a and 2b signals representing a binary number proportional to aselected maximum value for the per cent slip being measured by thesystem are generated by any suitable source such as a series ofthumbwheel-operated switches 90. The binary signals generated by thesetting of these switches 90 are applied to one set of inputs to acomparator 91. The other set of inputs to the comparator 91 receives thebinary signals digitally representing the number stored in the counter81, which is the measured per cent slip value. The output of thecomparator 91 is applied continuously to the data input of a D-typeflip-flop 92 via an inverter 93 and a NAND gate 94. At the end of eachoperating cycle, the flip-flop 92 is clocked to sample the comparatoroutput and thereby determine whether the measured percent slip value isabove or below the preselected maximumvalue. If the measured value isabove the preselected maximum value, the output of the flip-flop 92renders a transistor T1 conductive to energize a suitable alarm device,such as by energizing a relay coil, for example, to inform the operatorthat an excessive slip condition has been detected.

The signal for clocking the flip-flop 92 is designated GCLK (FIG. 8) andis generated at the end of each computation period. More specifically,the carry output signal CRY from the adder 75 is passed through aninverter 100 to a NAND gate 101 so that when the signal CRY drops to thebinary 0 level at the end of the division process, a binary l signal CRYis applied to the gate 101 so that it passes the clock signal CL2 toapply a signal GX (FIG. 8) to a NOR gate 102. The other input to thegate 102 is the signal SMC from gate 70, which is a binary 0 signalduring the computation period. Thus as can be most clearly seen fromFIG. 8, the output GCLK of the gate 102 goes to the binary 1 level whenthe signal GX drops to the binary 0 level, but after the signal SMCreturns to the binary I level at the end of the computation period theoutput signal GCLK from the gate 102 is held atthe binary 0 level and isno longer affected by transitions in the signal GX. Consequently, theoutput of the gate 102 forms a single positive-going pulse at the end ofeach computation period, and it is this output signal that is designatedsignal GCLK and used to clock the flip-flop 9-2. When the signalGCLKclocks the flip-flop 92, the complement of the binary signal present atthe data input is transferred to the Q output, which is applied to'aNAND gate so that the complement of the Q output is applied to the baseof the transistor T1.

If the output of the counter 81 does not exceed the number representedby the settings of the thumbwheel switches 90, the comparator output isa binary 0 signal so that a binary 0 signal is applied to the data inputof the flip-flop 92; consequently, a binary Q signal is applied to thebase of the transistor T1 to maintain the transistor T1 in anonconductive state. On the other hand, when the comparator output is abinary 1 signal, indicating that the output of the. counter 81 hasexceeded the limit set by the thumbwheel switches 90, the flip-flop 92causes a binary 1 signal to be applied to the base of the transistor T1,thereby rendering the transistor T1 conductive to actuatean alarm orother utilization device to indicate an excessive slip condition.

As still another feature of the invention, a counter overflow detectoris provided to turn on the transistor T1 in response to an overflow ofthe BCD counter 81. Without this feature the counter 81 could pass theexcessive slip value, reach its full capacity, and then reset itself andstart counting from zero so that the apparent count at the end of thecomputation period would be below the preselected maximum. Thus, if thecounter 81 overflows, a binary 1 signal is produced on an output line103 and passed through an inverter 104 to the clock input of a D-typeflip-flop 105, thereby producing a binary 0 signal at the Q output ofthe flip-flop 105. This binary 0 signal is applied to the NAND gate 94,thereby changing the output of the gate 94 from a binary 0 toabinary 1.Consequently, when the flip-flop 92 is closed by the GCLK signal goingto the binary 1 level at the end of the computation period, a binary 1signal is produced at the Q'output of the flip-flop 92 even though theapparent slip value represented by the count in counter 81 is below thepreselected maximum slip value represented by the settings of thethumbwheel switches 90. Thus, the transistor T1 isvrendered conductiveto actuate the excess slip alarm or other suitable utilization device.

In accordance with another specific aspect of the invention, a start-upcheck system is provided for detecting whether a predetermined number ofgenerator pulses P, are generated before the first motor pulse P,,,. Ifthey are, the motor is either not'starting or there is a malfunction inthe motor pulse generating system, so the system immediately activatesthe excess slip indicator or other utilization device so thatappropriate remedial action can be taken by the operator. Thus, thegenerator pulses P, are applied to a NOR gate whose other input is the Qoutput of a D-type flip-flop l l 1. The motor pulses P, are applied tothe clock input of another D-type flip-flop 112 whose data input is the0 output of the flip-flop 111.

When the system is started up, the generator pulses P, are passedthrough the gate 110 (signal UPF in FIG. 9) and an inverter 113 to theauxiliary counter unit 74 which counts the pulses and produces acorresponding output on a series of output lines indicated at 74a. A

selected combination of these output lines 74a are connected to a NANDgate 114 so that the gate 114 produces a binary signal LKOUT in responseto the counting of a predetermined number of generator 'puisem,riiisnaaryibmpm signal from the gate m clockinput to flip-flop 111. TheQ output signal STRT of the flip-flop 111 is applied to the gate 110toprevent the application of any further generator pulses P, to thecounter 74, while the Q output signal STRTis applied to the data inputof the flip-flop 112 to hold the Q output signal GO (FIGS. 4 and 9) ofthe flip-flop 1 12 at the binary 0 level. This binary 0 signal G0 ispassed through a NOR gate 115 to apply a binary 1 signal SOK (FIG. 9) tothe preset input of the flip-flop 111.

In order to actuate the alarm when no motor pulses P, have been receivedwithin the predetermined startup check interval, the Q output (GO) ofthe flip-flop 112 and the Q output (STRT) of the flip-flop 111 areapplied to a NAND gate 115 connected to the preset input of theflip-flop 92. Both the inputs to the gate 115 are thus binary 1 signals,producing a binary 0 output which overrides the synchronous inputs tothe flip-flop 92 to produce a binary 0 signal at the Q output andthereby turn on the transistor Tl. When a motor pulse P,, is received atthe clock inpu of the flip-flop 112 before the predetermined number ofgenerator pulses has been counted, the output of the gate 114 (signalLKOUT) is a binary 1 signal, producing a binary l at the data input tothe flip-flop 112 so that the arrival of P produces a binary 1 signal G0at the Q output of flip-flop 1 12. Thus, the Q output (GO) of theflip-flop 112 is a binary 0 signal which holds the output of the gate115 at the binary 1 level so that the flip-flop 92 is not preset. Thisprevents actuation of the alarm or other utilization device controlledby the transistor T1. At the same time, the switching of signal GO tothe binaryIO level enables the flip-flops 36 and 40 so that the systemis free tobegin measuring the period T,,,. The signal .60 also furnishesthe required binary 1 signal at the data inputs of the flipeflops 57 and64.

Yet another feature of the invention is the provision of monitoringmeans to ensure that both the motor and generator signals P and P, arepresent and remain present throughout operation of the system. Withoutsuch a check, the termination of one of these input signals due to amalfunction could result in a calculation of zero slip or some othererror which could mislead the operator. Thus, the two input signals Pand P, are applied-to a pair of monostable (single-shot) multivibrators120 and 121 through a pair of inverters 122 and 123, respectively.Whenthe multivibrators 120 and 121 are triggered bythe input signals,the respective outputs OS1 and 082 are switched from the binary 0 levelto the binary 1 level for predetermined intervals which are longer thanthe interval between a pair of successive pulses P 'and P,.Consequently, as long as both signals P,, and P, are pr'esent,'theoutput of a NAND gate 124 is a continuous binary 0 signal. This signalTPE (FIG. 10) is applied to the clock input of a D-type flip-flop 125which has a continuous binary 1 signal applied to its data input. In theevent'that either signal P, or P is not received within the interval ofthe binary 1 output of the multivibrator 121 or 120, respectively,signal TPE goes to the binary 1 level,

thereby clocking the flip-flop to produce a binary 1 signal FFB (FIG.10) at the Q output. This output is passed through an inverter 126,producing a binary 0 signal that is applied to the gate 95 to render thetransistor Tl conductive. That is, the gate 95 responds to the binary 0from inverter 126 to produce a binary l which is applied to the base ofthe transistor T1 to energize the alarm controlled thereby.

To reset the entire slip detection system after each operating cycle,i.e., at the end of each computation period, the signalGCL'K triggers amonostable (single shot) multivibrator 130 to generate reset signals RSTand RST (FIGS. 4 and 8). Thus signal GCLK is passed through an inverter131 to form'si'gnal GCLK, which is passed through a NAND gate 132 toform a signal LPST (FIG. 8). Signal LPST, in turn, is passed through aninverter 134 to fomi a signal SRT (FIG. 8) to trigger the multivibrator130. More specifically, when signal GCLK goes to the binary 1 level atthe end of the computation period, GCLK goes to the binary 0 level toswitch the output of gate 132 (signal LPST) to the binary 1 level,thereby switching signal SRT to the binary 0 level and signal SRT to thebinary I level which triggers the multivibrator 130. This causes the Qand Q output signals (RST and RST) of the multivibrator 130 to switch tothe binary l and 0 levels, respectively, for a predetermined interval,after which they automatically return to their normal binary 0 and 1levels.

The binary 1 signal RST is used to clear the JK-type flip-flops 36, 37,40 and 41 and the counters 52 and 74, while the binary 0 signal RST isused to clear the D- type flip-flops 57, 64 and 105. Thus, the binary 1signal RST is applied to the two NOR gates 38 and 39, thereby producingbinary 0 outputs (e.g., output signal CLEARX from gate 38, illustratedin FIG. 4) which are applied to the clear inputs of flip-flops 36, 37,40 and 41 tohold the Q outputs of these flip-flops at the binary 0 levelat least until signal RST returns to the binary 0 level. To clear thecounters 52 and 74, the signal RST is applied directly to the clearinputs thereof. Similarly, the binary 0 signal RST is applied directlyto the clear inputs of the Dv-type flip-flops 57, 64 and 105 to resetthese three units.

The reset signals RST and RST are also generated in response to twoother signals, AST or GST. The first of these signals, namely AST, is ananti-hang up signal produced to reset the system in case the register 65contains-a zero, so that the signal GCLK would never be generated. Thus,signal AST is generated whenever more than six transitions occur at theQ output (Pl-IA) of the flip-flop 37 before a transition occurs at the Qoutput PHAD of flip-flop 57'. To this end, a counter is incremented byone in response to each transition in signal PI-IA, and is reset eachtime signal PI-IAD goes from the binary 1 level to the binary 0 level.The 2 and4 output lines of the counter 140 are connected to a NAND gate141, indicating the occurrence of six transitions insignal PI-IA. If abinary 1 signal appears on both of these counter output lines before theoccurrence of a negative transition in signal PI-IAD, the output of thegate 141 goes from the binary 1 level to the binary 0 level. This binary0 signal is applied to the NAND gate 132 which normally receives abinary l signal GCLK so that the gate output LPST becomes a binary 1signal. This binary 1 signal LPST is passed on through the NOR gate 133and the inverter 134 to apply a binary 1 signal to the multivibrator130,

. 1 9 thereby triggering the multivibrator to generate the reset signalsRST and RST.

Signal GST generates the reset signals whenever the power is turned onto the system. Thus, the power is turned on by closing a switchS1,.thereby charging a capacitor C3 through a resistor R3 from a voltagesource V1. When the capacitor C3 is charged to a predetermined level, azener diode D1 becomes conductive to render a transistor T2 conductive.This generates a 1 signal GST at one of theinputs to the NOR gate 123 totrigger the multivibrator 120 and thereby reset the system in the manneralready described above.

To ensure actuation of the alarm in response to an excess slip conditionor any of the malfunctions described above, the reset signals RST andRST do not reset any of the alarm-actuating components; a separatesystem is provided for resetting these components in response to thepower on signal GST or an external reset command signal. Morespecifically, the reset signals RST and RST do-not' reset any of theflip-flops 92, 111, or 125 which control actuation of the alarm viatransistor T1. To reset these flip-flops whenever the power supply tothe system is'turned on by closing the switch S1, the binary 1 signal(GST) from the transistor T2 triggers a monostable single-shotmultivibrator 150 to generate a binary 1 signal for a predeterminedinterval at the Q output (signal FFR) and a binary signal for apredetermined interval at the Q output (signal FFR, FIG. 9). The signalFFR clears the flip-flops 92, 112 and 125 (the latter via inverter 151),while the signal FFR clears the flip-flop 111 via NOR gate 115.

To permit resetting of the entire system while the power is on, thereset signals FFR and FFR may also be generated in response to anexternal reset command signal. For example, it may be desired togenerate such signals when the slip detector is switched from onealternator to another. In the system of FIGS. 2a and 2b,

' the means for initiating a reset command signal is exemplified by aswitch S2 connected between a voltage source V2 and the base of atransistor T3. When closed, the switch S2 renders a transistor T3conductive via diode D2, and the resulting signal PST (FIG. 10) at thecollector of the transistor T3 triggers the single shot 150 to generatethe reset signals FFR and FFR and thereby reset the flip flops 92, 111,112 and 125.

As can be seen from the foregoing detailed descrip- .tion, thisinvention provides a step detection system which continuously monitorsthe per cent slip between the motor and the generator, and actuates autilization device such as an alarm or automatic shut-down devicewhenever the slip exceeds a predetermined limit. The

system has a high degree of accuracy and reliability over a wide speedrange, and the thumbwheel switches permit convenient manual adjustmentof the predetermined slip limit. The system continually computes the percent slip and provides a substantially instantaneous indication ofwhether the per cent slip is above or below the predetermined limit, andis characterized by high reliability and immunity from aging or drift byvirtue of the digital signal processing on-a rapidly iterating basis. Inaddition, thesystem immediately senses a failure of the motor to startand provides an indication of suchv failure, and also continuouslymonitors the primary inputs to the system and provides a substantiallyinstantaneous indication of any malfunction that results in aninterruption of such inputs.

What is claimed is: 1. A system for detecting excessive slip between thespeed of an a-c. motor and the speed of an a-c. generator supplyingpower to said motor at a variable fre- 5 quency, said system comprisingthe combination of a. means for generating a first electrical signalrepresenting the speed of the generator,

b. means for generating a second electrical signal representing thespeed of the motor,

0. means for generating a third electrical signal representing apreselected maximum limit for thepercentage of slip between saidgenerator and said motor,

d. computing means responsive to said first and second signals forproducing an electrical output signal representing K(N m)/N,, where K isa predetermined constant, N, is the generator speed, and N is the motorspeed,

e. and means responsive to said third signal and said output signal forproducing an excess slip output signal whenever the value represented bysaid output signal exceeds the preselected limit represented by saidthird signal. 2. A system for detecting excessive slip as set forth inclaim 1 wherein said means for generating said first electrical signalcomprises means for generating pulses at a frequency proportional to thegenerator speed, and said means for generating said second electricalsignal comprises means for generating pulses at a frequency proportionalto the motor speed.

3. A system for detecting excessive slip as set forth in claim 2 whereinsaid computing means includes 1. means responsive to said first signalfor producing an electrical signal digitally representing a numberproportional to the duration of the period T be tween pulses in saidfirst signal,

2. means responsive to said second signal for producing an electricalsignal digitally representing a number proportional to the duration ofthe period T,, between pulses in said second signal,

3. and means responsive to said T and T,,, signals for producing anelectrical signal digitally representing a number proportional to K( TT,,)'/T,,,.

4. A system for detecting excessive slip as set forth in claim 3 whereinsaid means for producing said signal representing a number proportionalto K( T ,,)/T,,,=

includes a source of clock pulses, an up-down counter having count-upand count-down input terminals and an output terminal, means forapplying said clock pulses to the count-up input terminal of saidcounter during the period m, and means for applying said clock pulses tothe count-down input terminal of said counter during the period T, forproducing an electrical signal at the counter output terminal digitallyrepresenting a number proportional to the difference (T,, T

5. A system for detecting excessive slip as set forth in claim 3 whereinsaid means for producing said signal digitally representing a numberproportional to K( T, T,,)/T comprises 1. means for generating anelectrical signal digitally representing a number proportional to thedifference (T T i 2. means responsive to said signalsdigitally'representing numbers proportional to (T and T,,,

' for repetitively subtracting the number proportional to T from thenumber proportional to (T,,, until the remainder is reduced to zero,

said output signal.

3. and means for counting the number of subtraction steps required toreduce said remainder to zero.

6. A system for detecting excessive slip asset forth in claim whereinsaid means for producing said signal representing a number proportionalto (7",, T includes anup-down counter, and means for recycling anelectrical signal digitally representing the remainder from each of therepetitive subtraction steps to said counter for use as the minuend inthe next subtraction step.

7. A system for detecting excessive slip as set forthin claim 5 whereinsaid means for repetitively subtracting the number'proportional to T,from thenumber proportionalto (T,, T comprises means for producing anelectrical signal digitally representing the twos complement of a binarynumber proportional to T and adding means for producing an electricalsignal digitally representing the sum of said twos complement and abinary number proportional to (T,,, T

8. Asystem for detecting excessive slip as set forth in claim 7 whereinsaid adding means is a binary adder having a carry output, and includingan electronic counter connected to saidcarry output for counting thenumber of addition steps which yield a carry to produce an electricalsignal digitally representing a number proportional 'to. the quotient (Tg)/T,,,.

. 9. A system for detecting excessive slip as set forth in claim 1wherein said means for generating said third signal includes a set ofmanually operable switch means for selecting said maximum limit.

10. A system for detecting excessive slip as set forth in claim 1wherein said means for producing an excess slip signal comprises acomparator for comparing said third signal and said output signal.

11. A system for detecting excessive slip as set forth in claim 2 whichincludes means for producing a start signal in response to generation ofthe first pulse in said second signal within a'predetermined intervalfollowing generation of the first pulse in said first signal, and meansfor activating a utilization device in response to the absence of saidstart signal after said predetermined interval. 3

12. A slip detection system as set forth in claim 5 which includesoverflow detection means for activating a utilizationdevice in responseto an overflow of said counter.

13. A slip detection system as set forth in claim 1 which includes meansfor monitoring said signals representing the speeds of the motor andgenerator, means for producing an output signal in responsetotermination of either of said speed-representing signals, and means foractivating a utilization device in response to 14. A slip detectionsystem as set forth in claim 1 which includes internal reset means forautomatically resetting said system at the end of each cycle ofoperation of said computing means, and means responsive to production ofsaid excess slip signal prior to the resetting operation for maintainingsaid excess slip signal during and subsequent to the resettingoperation.

15. A slip detection system as set forth in claim 1 which includesexternal reset means responsive to a command signal for resetting theentire slip detection. system including the means for producing saidexcess slip signal.

16. A slip detection system as set forth in claim which includes meansresponsive to the absence of either of said speed-representing signalsat startup of the system for activating a utilization device. I

17. A system for signaling the percentage differencebetween'tworecurring signals having variable periods,

said system comprising the combination of a. an up-down counter having acount-up input terminal, a count-down input terminal, and outputterminals carrying electrical signals digitally representing the numbercontained in the counter,

b. a source of clock pulses,

c. means responsive'to a first one of said recurring signals forapplying said'clock pulses to said countup input terminal during oneperiod of said first signal to produce counter output signals digitallyrepresenting a number T,, proportional to the duration of said oneperiod of said first signal,

d. means'responsive to the second recurring signal for applying saidclock pulses to said count-down input terminal during one period of saidsecond signal to produce counter output signals digitally representing anumber K( 7",, T,,) proportional to the difference between the durationsof the periods of said first and second signals,

e. subtracting means responsive to said output signals digitallyrepresenting said numbers T and K( T,,

I T for producing output signals digitally representing thedifference K(T T,,,,

f. means for repetitively applying said difference output signals fromsaid subtracting means and said signals representing said number T, tosaid subtracting means until the output signals therefrom represent azero difference,

g. a source of clock pulses generated at the same frequency at whichsaid differenceoutput signals are repetitively applied to saidsubtracting means,

h. and an electronic counter for counting the clock pulses from source(g) and producing output signals digitally representing the number ofsubtraction operations required to reduce the difference represented bythe output signals from said subtracting means to zero, whereby theoutput signals from said counter digitally represent the quotient of nza)/ m- 18. A system as set'forth in claim 17 wherein said subtractingmeans comprises means for producing'electrical signals digitallyrepresenting the twos complement of a binary number T,,,, and addingmeans for producing an electrical signaldigitally representing the sumof said twos complement and a binary number K( m u)- I 19. A system asset forth in claim 18 wherein said adding means is a binary adder havinga carry output for producing a carry output signal as long as said sumis greater than zero, and including means responsive to said carryoutput signal for applying the clock pulses from source (g) to saidcounter only until said sum is reduced to zero. A

20. A method for detecting excessive slip between resenting the speed ofthe motor,

1. A system for detecting excessive slip between the speed of an a-c.motor and the speed of an a-c. generator supplying power to said motorat a variable frequency, said system comprising the combination of a.means for generating a first electrical signal representing the speed ofthe generator, b. means for generating a second electrical signalrepresenting the speed of the motor, c. means for generating a thirdelectrical signal representing a preselected maximum limit for thepercentage of slip between said generator and said motor, d. computingmeans responsive to said first and second signals for producing anelectrical output signal representing K(Ng Nm)/Ng where K is apredetermined constant, Ng is the generator speed, and Nm is the motorspeed, e. and means responsive to said third signal and said outputsignal for producing an excess slip output signal whenever the valuerepresented by said output signal exceeds the preselected limitrepresented by said third signal.
 2. A system for detecting excessiveslip as set forth in claim 1 wherein said means for generating saidfirst electrical signal comprises means for generating pulses at afrequency proportional to the generator speed, and said means forgenerating said second electrical signal comprises means for generatingpulses at a frequency proportional to the motor speed.
 2. meansresponsive to said second signal for producing an electrical signaldigitally representing a number proportional to the duration of theperiod Tm between pulses in said second signal,
 2. means responsive tosaid signals digitally representing numbers proportional to (Tm - Tg)and Tm for repetitively subtracting the number proportional tO Tm fromthe number proportional to (Tm - Tg) until the remainder is reduced tozero,
 3. and means for counting the number of subtraction steps requiredto reduce said remainder to zero.
 3. and means responsive to said Tg andTm signals for producing an electrical signal digitally representing anumber proportional to K(Tm - Tg)/Tm.
 3. A system for detectingexcessive slip as set forth in claim 2 wherein said computing meansincludes
 4. A system for detecting excessive slip as set forth in claim3 wherein said means for producing said signal representing a numberproportional to K(Tm - Tg)/Tm includes a source of clock pulses, anup-down counter having count-up and count-down input terminals and anoutput terminal, means for applying said clock pulses to the count-upinput terminal of said counter during the period Tm, and means forapplying said clock pulses to the count-down input terminal of saidcounter during the period Tg for producing an electrical signal at thecounter output terminal digitally representing a number proportional tothe difference (Tm - Tg).
 5. A system for detecting excessive slip asset forth in claim 3 wherein said means for producing said signaldigitally representing a number proportional to K(Tm - Tg)/Tm comprises6. A system for detecting excessive slip as set forth in claim 5 whereinsaid means for producing said signal representing a number proportionalto (Tm - Tg) includes an up-down counter, and means for recycling anelectrical signal digitally representing the remainder from each of therepetitive subtraction steps to said counter for use as the minuend inthe next subtraction step.
 7. A system for detecting excessive slip asset forth in claim 5 wherein said means for repetitively subtracting thenumber proportional to Tm from the number proportional to (Tm - Tg)comprises means for producing an electrical signal digitallyrepresenting the two''s complement of a binary number proportional toTm, and adding means for producing an electrical signal digitallyrepresenting the sum of said two''s complement and a binary numberproportional to (Tm - Tg).
 8. A system for detecting excessive slip asset forth in claim 7 wherein said adding means is a binary adder havinga carry output, and including an electronic counter connected to saidcarry output for counting the number of addition steps which yield acarry to produce an electrical signal digitally representing a numberproportional to the quotient (Tm - Tg)/Tm.
 9. A system for detectingexcessive slip as set forth in claim 1 wherein said means for generatingsaid third signal includes a set of manually operable switch means forselecting said maximum limit.
 10. A system for detecting excessive slipas set forth in claim 1 wherein said means for producing an excess slipsignal comprises a comparator for comparing said third signal and saidoutput signal.
 11. A system for detecting excessive slip as set forth inclaim 2 which includes means for producing a start signal in response togeneration of the first pulse in said second signal within apredetermined interval following generation of the first pulse in saidfirst signal, and means for activating a utilization device in responseto the absence of said start signal after said predetermined interval.12. A slip detection system as set forth in claim 5 which includesoverflow detection means for activating a utilization device in responseto an overflow of said counter.
 13. A slip detection system as set forthin claim 1 which includes means for monitoring said signals representingthe speeds of the motor and generator, means for producing an outputsignal in response to termination of either of said speed-representingsignals, and means for activating a utilization device in response tosaid output signal.
 14. A slip detection system as set forth in claim 1which includes internal reset means for automatically resetting saidsystem at the end of each cycle of operation of said computing means,and means responsive to production of said excess slip signal prior tothe resetting operation for maintaining said excess slip signal duringand subsequent to the resetting operation.
 15. A slip detection systemas set forth in claim 1 which includes external reset means responsiveto a command signal for resetting the entire slip detection systemincluding the means for producing said excess slip signal.
 16. A slipdetection system as set forth in claim 1 which includes means responsiveto the absence of either of said speed-representing signals at start-upof the system for activating a utilization device.
 17. A system forsignaling the percentage difference between two recurring signals havingvariable periods, said system comprising the combination of a. anup-down counter having a count-up input terminal, a count-down inputterminal, and output terminals carrying electrIcal signals digitallyrepresenting the number contained in the counter, b. a source of clockpulses, c. means responsive to a first one of said recurring signals forapplying said clock pulses to said count-up input terminal during oneperiod of said first signal to produce counter output signals digitallyrepresenting a number Tm proportional to the duration of said one periodof said first signal, d. means responsive to the second recurring signalfor applying said clock pulses to said count-down input terminal duringone period of said second signal to produce counter output signalsdigitally representing a number K(Tm - Tg) proportional to thedifference between the durations of the periods of said first and secondsignals, e. subtracting means responsive to said output signalsdigitally representing said numbers Tm and K(Tm - Tg) for producingoutput signals digitally representing the difference K(Tm - Tg) - Tm, f.means for repetitively applying said difference output signals from saidsubtracting means and said signals representing said number Tm to saidsubtracting means until the output signals therefrom represent a zerodifference, g. a source of clock pulses generated at the same frequencyat which said difference output signals are repetitively applied to saidsubtracting means, h. and an electronic counter for counting the clockpulses from source (g) and producing output signals digitallyrepresenting the number of subtraction operations required to reduce thedifference represented by the output signals from said subtracting meansto zero, whereby the output signals from said counter digitallyrepresent the quotient of K(Tm - Tg)/Tm.
 18. A system as set forth inclaim 17 wherein said subtracting means comprises means for producingelectrical signals digitally representing the two''s complement of abinary number Tm, and adding means for producing an electrical signaldigitally representing the sum of said two''s complement and a binarynumber K(Tm - Tg).
 19. A system as set forth in claim 18 wherein saidadding means is a binary adder having a carry output for producing acarry output signal as long as said sum is greater than zero, andincluding means responsive to said carry output signal for applying theclock pulses from source (g) to said counter only until said sum isreduced to zero.
 20. A method for detecting excessive slip between thespeed of an a-c. motor and the speed of an a-c. generator supplyingpower to said motor at a variable frequency, said method comprising thesteps of a. generating a first electrical signal representing the speedof the generator, b. generating a second electrical signal representingthe speed of the motor, c. generating a third electrical signalrepresenting a preselected maximum limit for the percentage of slipbetween said generator and said motor, d. producing an electrical signalin response to said first and second signals and representing K(Ng -Nm)/Ng where K is a predetermined constant, Ng is the generator speed,and Nm is the motor speed, e. rapidly iterating steps (a) through (d),f. and producing an excess slip signal in response to said third signaland said output signal whenever the value represented by said outputsignal exceeds the preselected limit represented by said third signal.21. A method for detecting excessive slip as set forth in claim 20wherein said first signal comprises pulses generated at a frequencyproportional to the generator speed, and said second signal comprisespulses generated at a frequency proportional to the motor speed.
 22. Amethod for detecting excessive slip as set forth in claim 21 includingthe steps of producing an electrical signal digitally representing anumber proportional to the period Tg between pulses in said firstsignal, producing an electrical signal digitally representing a numberproportional to the period Tm between pulses in said second signal, andproducing an electrical signal digitally representing a numberproportional to K(Tm - Tg)/Tm in response to said Tg and Tm signals. 23.A method for detecting excessive slip as set forth in claim 22 whereinsaid signal representing a number proportional to K(Tm - Tg)/Tm isproduced by generating a series of clock pulses, applying said clockpulses to the count-up input terminal of an up-down counter during theperiod Tm, and applying said clock pulses to the count-down inputterminal of said counter during the period Tg for producing anelectrical signal digitally representing a number proportional to thedifference (Tm - Tg).
 24. A method for detecting excessive slip as setforth in claim 22 wherein said signal representing a number proportionalto K(Tm - Tg)/Tm is produced by generating an electrical signaldigitally representing a number proportional to the difference (Tm -Tg), repetitively subtracting the number proportional to Tm from thenumber proportional to (Tm - Tg) until the remainder is reduced to zero,and counting the number of subtraction steps required to reduce saidremainder to zero.
 25. A method for detecting excessive slip as setforth in claim 24 wherein the repetitive subtraction is carried out byproducing an electrical signal digitally representing the two''scomplement of a binary number proportional to Tm, and producing anelectrical signal digitally representing the sum of said two''scomplement and a binary number proportional to (Tm - Tg).
 26. A methodfor detecting excessive slip as set forth in claim 24 wherein theremainder from each of the repetitive subtraction steps is used as theminuend in the next subtraction step.
 27. A method for detectingexcessive slip as set forth in claim 24 which includes the step ofactivating a utilization device in response to the counting of a numberof subtraction steps above a predetermined limit.
 28. A method fordetecting excessive slip as set forth in claim 25 wherein the signalrepresenting a number proportional to the quotient (Tm - Tg)/Tm isgenerated by counting the number of binary addition steps which yield acarry.
 29. A method for detecting excessive slip as set forth in claim21 which includes the steps of producing a start signal in response togeneration of the first pulse in said second signal within apredetermined interval following generation of the first pulse in saidfirst signal, and activating a utilization device in response to theabsence of said start signal after said predetermined interval.
 30. Amethod for detecting excessive slip as set forth in claim 20 whichincludes the steps of monitoring said signals representing the speeds ofthe motor and generator, producing an output signal in response totermination of either of said speed-representing signals, and activatinga utilization device in response to said output signal.
 31. A method fordetecting excessive slip as set forth in claim 20 which includes thestep of activating a utilization device in response to the absence ofeither of said speed-representing signals at start-up.